1. Technical Field
The present invention relates to a successive-approximation-register (SAR) analog-to-digital converter (ADC), and more particularly, to an SAR ADC for programmably amplifying amplitude of an input signal and a method thereof.
2. Related Art
An analog-to-digital converter (ADC) has multiple architectures, such as a flash ADC, a pipelined ADC and a successive-approximation-register (SAR) ADC. Each architecture has its own advantages and is generally selected according to different application requirements. In comparison with other architectures, the SAR ADC consumes less power, while occupying smaller area and incurring a lower cost.
The operation of the SAR ADC starts from a sampling phase. During the sampling phase, a sample-and-hold (S/H) circuit samples and accesses an analog input signal. Next, the SAR ADC enters a bit-cycling phase (bit-cycling phase), to decide transformation output of a digital code.
An N-bit SAR ADC generally includes an S/H circuit, an N-bit digital-to-analog converter (DAC), a voltage comparator and an SAR control circuit.
An input voltage provides a stable voltage to the voltage comparator through the S/H circuit, and the voltage comparator compares the stable voltage with an output voltage of the N-bit DAC. The SAR control circuit controls an output of the N-bit DAC by using a binary search algorithm.
The S/H circuit and the N-bit DAC are generally implemented by a capacitive DAC formed by a capacitor array. The SAR control circuit adjusts the output of the N-bit DAC by controlling switching of a switch element in the capacitive DAC.
In order to suppress power supply noise and common-mode noise, a common SAR ADC adopts a full differential structure. There mainly exist two types of common SAR ADCs with the full differential structure: one performs sampling by adopting a top plate, and the other performs sampling by adopting a bottom plate. That is to say, during the sampling phase, the top plates of the capacitor array are coupled to an input signal or the bottom plates of the capacitor array are coupled to an input signal, so as to sample the input signal.
Due to limitation of sampling noise (KT/C noise), of a capacitor, the size of a sampling capacitor of the SAR ADC is generally inversely proportional to the square of the amplitude of the input signal. Consequently, if the amplitude of the input signal can be increased, the size of the sampling capacitor may be greatly reduced. In the prior art, a programmable gain amplifier (PGA) is mainly used to amplify the amplitude of the input signal, but the PGA itself occupies the area of a chip, and contributes extra noise.